Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Well, it stands for Power-On-Reset. This sort of circuit "enables" any other circuits inside the chip. In other words when VDD goes above the safety minimum level of operation for the other circuits then VDD is applied to them, and when VDD drops below the safety minimum required voltage level for proper operation, the POR circuit disables other circuits inside the chip and so ensures proper operation (or no operation at all). The POR circuit also generates a reset pulse for all digital circuits inside the chip and ensures a delay before applying VDD for allowing to reset pulse to be distributed around all digital blocks.
The POR layer is the "Passivation Opening" layer that is placed on the pads to create the opening for the bond wire. Without this layer, the pad would be covered with passivation and would make it imposible to connect the bond wire to the IC.