1. source latency is the propagation time from the actual clock origin to the clock
definition point in the design;
2. network latency is the porpagation time form the clock definition point in the design to DFF's clk.
when pre-layout: you must set_clock_latency -source .... and
set _clock_latency ......
when post-layout you must set_clock_latency -source .... and
set _propagated_clock ......
tools can auto calculate the network latency.
basically, the clock latency is the delay from the clock root pin (clock source) to the clock leaf pin (such as clock pin of a DFF). Different clock leaf pin may have different latency, which is clock skew.
In design, during pre-layout, you will need to set the clock latency you expected. And after layout, you will need to let the STA tools to calculate each leaf pin's latency and see if there any timing issues caused by the latency.
"set_clock_latency" defines the estimated clock
insertion delay during synthesis.
This is primarily used during the pre-layout synthesis and timing analysis.
After layout, "set_propagated_clock" will make EDA tools calculate the clock latency and skews.