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What does "elaborate design" in lec do

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narureddyk

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Does the "elaborate design" in LEC do any synthesis? does it generate any netlist?because in my lec dofile has the following steps
read design .............
elaborate design -golden
set root module abc_core -golden
read design -verilog
xyz_lec.v
-revised -lastmod
set root module abc_core -revised
Can any one explain what this lec step is doing and whuch netlistls it is comparing?
 

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