What does delta delay mean?

[rajakash]

wat is mean by delta delay?

 

[rakesh_aadhimoolam]

Re: delta delay

Refer VHDL by Charles Roth.........

you find a detail description on Delta Delay..............

if you don't have the book...i would expalin it in next reply...............


good luck

 

[sheik_vb]

Re: delta delay

Hi,
I don't have the book. Please reply.

 

[haneet]

Re: delta delay

I am aware of VHDL and not Verilog and so im going to tell w.r.t VHDL. Delta delay is infinitesimal delay. This delay occurs with signal when the values are assigned. this is the reason u will observe at times the value assigned by the signal is not assigned immediately to the resultant but after some delay and this delay is known as delta delay.

 

[sachingorkhe]

Re: delta delay

Delta Delay:-

Delta Delay is the default signal assignment propogation delay if there no delay is explicitly prescribed.
Delta is an infinitesimal VHDL time unit so that all signal assignments can result in signals assuming their values at a future time.
e.g.-
output <= NOT input; -- output assumes new value in one delta cycle.

 

[vinodkumar]

Re: delta delay

hi,
As iam is concerned delta delay,tansport delay and others various ways of modeling the delays.

when we r declaring as a signal it assigns the updated value in the next clock cycle.thts the diff between var and sig,if u would like to change the value at the same clock use var otherwise sig.

variable we will not get any where whereas sig we will get HW.so delay modeling.

 

[nand_gates]

Re: delta delay

See this ...

https://www.people.vcu.edu/~rhklenke/tutorials/vhdl/modules/m10_23/sld043.htm

VHDL is a concurrent laguage (it has to be since it represents simultaneously
working digital gates). The problem arises when you try to mimic this concurrent
behaviour in VHDL simulator which is written in C and executes sequencially.
consider following VHDL statements representing two AND gates.

We execute them in C

y <= a and d;
d <= b and c;

say a= '1' c = '1' and b = '0' d will be '0' so y='0'
now if b changes from '0' -> '1'
and we evaluate abouve statement as it is we still get y = '0'

If we write the above statements as

d <= b and c;
y <= a and d;

and execute sequencially we get y= '1' the correct answer. Just in one pass.

This shows that in C the order of execution will change the final result.
In order to solve this we have following iterative algorithm which will
give same result irrespective of the order in which the statements are executed.

1. wait for event on input. delta = 0
2. eveluate the statements with new values.
3. check for RHS variables if there is a cahange in any variable delta = delta+1 go to step 2.
else go to step 4.
4. done advance simulation time to get next event.

So the delta cycle means how many iteration happems in 0 simulation time in order to get all
the RHS variables stable.

Hope this helps..