What does decimation mean in Sigma-Delta ADCs?

[D.A]

What does decimation mean in Sigma-Delta ADCs?
I thought that the output signals from Sigma-Delta is 1bit long (PWM).
Does decimation make this PWM - multi bit sinal, which could be proccessed via DSP?

 

[Dmitrij]

Re: decimation

The general definition of decimation is decreasing the sampling frequency of the signal. These operation is usually done in the integer amount of times. Matlab has the special function decimate(), available in Command Window for getting further instructions of its use.

So it won't take much of your time, if you open Matlab and search this function in it's vast and rich Help. No doubt, you'll find many useful facts on your question.

With respect,

Dmitrij

 

[ieropsaltic]

Re: decimation

Delta-sigma ADCs belong to the oversampling data converters family which rely on increasing the sampling rate siginificantly above nyquist rate to reduce the quantization noise floor value ,thus on filtering, overall quantization noise decreases which is equivalent to higher number of bits. After filtering, it is usually required to drop back to the required (Nyquist) rate. Decimation process involves dropping the sampling rate . You can refer to Motorola notes "principles of delta-sigma modulators for ADCs" page 7-2

 

[cydi]

decimation

Decimation is absically a reduction of sampling time. In sigma delta, the simplest explanation would be: take the multiple single-bit data and combine it to a multibit one. It is much complicated than this, but this is the principle..