What does clock tree levels mean?

[shelkerahul]

Hi,


Can somebody tell me what CLOCK TREE LEVELS exactly means? And how OCV affect more, if levels are more ?

Thanks

 

[joe2moon]

Re: OCV

The "level" of clock tress means the number of clock buffer from the clock root to its sync pins.

For example, if the clock root is CLK_IN, and one of the sync pin is U_CORE/U_DSP/U_ALU/add_reg_1/CK.
And the path from the CLK_IN port to this CK pin is
CLK_IN --> U_CLK_01 (CLKBUFX12) --> U_CLK_02 (CLKBUFX8) --> CK-pin
Then the level is "2".
-----------------------------------------------------------------------------------------------

OCV: On-chip-variation
===============
If the level of one clock tree is longer than another one, then it may contain more type of clock buffers, such as X1, X2, X3, X4, X8, X12, X20 ....., and those clock buffers may distribute more widely over this chip.

==> More type of cell: More variations...
==> Wide range of chip: More variations...

 

[luancao]

OCV

CLOCK TREE LEVELS is the level of hirachies of the leaf trees. And in each clock tree level, there are serveral clock buffers.

For example, in the layout, you have two seperate block in the same clock domain. You could design your clock in such a way that the top level of the clock tree is from the clock root and then seperates into two branch each of the branch goes to one of the blocks in the clock domain. Then in each of the block, there are serveral or one level of branches. Say in one block the clock tree have 4 levels of branches. And in another, has 3 levels. We say the clock tree level is 4+2=6 levels.

OCV: On-chip-variation is the variation on the same chip by the PVT difference. Often hard to predict. But we know that if the chip is larger the OCV will be larger since the Process, IR drop and temperature will be more or less the same is your die is small. If the die is very big the power and ground pin, the clock tree and the functional related blocks should be put together. Flip chip should be used in this case.