Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What do you need to cover in STA ?

Status
Not open for further replies.

omara007

Advanced Member level 4
Joined
Jan 6, 2003
Messages
1,237
Helped
50
Reputation
102
Reaction score
16
Trophy points
1,318
Location
Cairo/Egypt
Activity points
9,715
Hi guys ..

What are the main things that you need to do in the STA phase ? .. I mean what else other than setup time and hold time ?
 

coolrak

Member level 4
Joined
Aug 16, 2005
Messages
73
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,989
Along with set-up and hold we also do maxcap, max trans, etc type of analysis
 

omara007

Advanced Member level 4
Joined
Jan 6, 2003
Messages
1,237
Helped
50
Reputation
102
Reaction score
16
Trophy points
1,318
Location
Cairo/Egypt
Activity points
9,715
coolrak said:
Along with set-up and hold we also do maxcap, max trans, etc type of analysis

would you please explain these terms ?
 

arunragavan

Advanced Member level 1
Joined
Jul 1, 2004
Messages
415
Helped
30
Reputation
60
Reaction score
9
Trophy points
1,298
Location
India
Activity points
5,028
i think he ment setuptime / holdtime maximum capacitance and maximum transconductance..

i have a small npresentation on STA.. wud upload it as soon as i find it.. wud end it in the same post..

with regards,
arun
 

coolrak

Member level 4
Joined
Aug 16, 2005
Messages
73
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,989
Hi Omara,

Every technology has some limitations and the foundry specifies them to consider

them while designing. normally vendor specifies the maxcap,maxtrans and maxfanout

load values and in STA we make sure we dont violate these values for each node.

These are the different checks

 Capacitance:
 Maximum allowed node capacitance (max_capacitance)
 Minimum allowed node capacitance (min_capacitance)

Transition:
 Maximum allowed signal transition (max_transition)
 Minimum allowed signal transition (min_transition)


Fanout:
 Maximum allowed fanout load (max_fanout)
 Minimum allowed fanout load (min_fanout)
 

omara007

Advanced Member level 4
Joined
Jan 6, 2003
Messages
1,237
Helped
50
Reputation
102
Reaction score
16
Trophy points
1,318
Location
Cairo/Egypt
Activity points
9,715
arunragavan said:
i think he ment setuptime / holdtime maximum capacitance and maximum transconductance..

i have a small npresentation on STA.. wud upload it as soon as i find it.. wud end it in the same post..

with regards,
arun

waiting for your presentation ..
 

arunragavan

Advanced Member level 1
Joined
Jul 1, 2004
Messages
415
Helped
30
Reputation
60
Reaction score
9
Trophy points
1,298
Location
India
Activity points
5,028
Ok dude.. here you go.. ive attached a copy of the STA presentation.. its kind extensive and hope it wud help you..
share you feedback on STA.. its very important.. and timing closure has to be meet..

enlighten us with your knowledge on STA..


with regards,
arun
 

    omara007

    Points: 2
    Helpful Answer Positive Rating

anjali

Full Member level 3
Joined
Aug 16, 2005
Messages
173
Helped
14
Reputation
28
Reaction score
6
Trophy points
1,298
Activity points
3,033
during STA, we need to check setup and hold, recovery and removal checks, DRCs, MAX/MIN path delays, etc..
 

eda_freak

Member level 3
Joined
Jun 20, 2005
Messages
62
Helped
12
Reputation
24
Reaction score
2
Trophy points
1,288
Activity points
1,997
Read the book by himanshu bhatnagar on ASIC and systhesis...its gr8...and u can easily download it from this forum....in case ur unable to find it u can contact me and il mail u a soft copy....
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top