What do you gain from Verilog2001 ?

[joe2moon]

Verilog2001 has added a lot of features/properties to make it can do things that VHDL can do, such as "signed" operation and multi-dimensional array.

Although the EDA venders, just like $ynopsys, C@dence, Ment0r, ... etc. all calim they will support Verilog2001 standard.
But in order to be portable to older veriosn Verilog simulator or logic synthesizer, I still use the subset of Verilog1995 to do my design.

I am wondering if you can really gain something from Verilog2001 ? 8O

 

[mami_hacky]

Verilog2001

Simply, I could obtain a better shape for my verilog code. I do not have to repeat the port list agian after module definition!

 

[walkon]

I think so , at least, it is possible for us to define the multi-dimension array and define an array of real numbers.

 

[echo47]

I build array processors in FPGA. The Verilog 2001 'generate' statement makes my source code extremely compact, and easy to adjust the number of processing stages.

 

[zzczx]

@ *, will never warry about the incompletely sensitivity list [/quote]

 

[gaonkc]

New future is good for write behavior model or test bench. such as new system task etc.

 

[ymli]

Actually I forget the new features of Verilog 2001 for the compatiblity reason.

 

[AlexWan]

hi,
Because those EDA vendors don't support V2K very well. Such as MD, if simulation tools and synthesis tools support it, I think I will to use those in my designs.

 

[troops]

which vendor surport VERILOG 2001 ??
is it same as system verilog ???