What do we need to look into a Design compiler synthesis report ?

[mr_vasanth]

What are the errors/warnings/messages we should give a careful attention in a DC-synthesis report ?
I have listed down few that I could recollect.
1. Any unmapped components
2. latches
3. non-resettable FFs
What else one has to look at and why ?
Any practical experience, which you missed to look at the synthesis report initially and found the issue later would be much appreciated.

Note that I am not talking about timing report, area report or power report here.

 

[rca]

- missing signal in sensitivity list
- check timing constraints
- check clock gating insertions
- check scan insertion
- check number of latch (if as expected)
-....

personnaly, non-resettable FFs could be normal to used smallest area flop.