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POST - routing ( a terminology similar to POST - layout i guess ) definately affects ur timing .... routing is the actual implementation of ur design ( hw its gonna come on the silicon) and hence the extact delays of the nets will be known only after that !!
during the pre-layout, the delays of the net is obtained frm wire-load models ( so u only get approxiomate timing closure values) , but only after placing & routing ur design, u get the real "net" values, so u hv to perform a "STA" after the routing as well !!!
parasitics extraction will be done only on the placed and routed netlist !!
so with this extracted values, u hv to perform a post-layout/route STA as well !!