What do u mean by design for verification

[harshad]

What do u mean by design for verification

 

[arthur]

I suggest two books for your reference.
1. Writing testbenches : functional verification of HDL models
2.Principles of verifiable RTL design : a functional coding style supporting verification processes in Verilog

 

[Robin_zhu]

DFV is a very fashion concept. I used to attend a synopsys seminar trageted on verification. They advacate SystemVerilog for implementing DFV idea.

 

[optor]

Maybe the Synopsys online document can help you.
visit the https://www.synopsys.com

 

[harshad]

Thanks for the replies


Useless.
Warning!

 

[gentle_man]

where can i find this book "Writing testbenches : functional verification of HDL models"

thanks

 

[spauls]

It is basically verification of RTL (Chip) using standard verifiction methods by creating TEST BENCHES in HVL(Hardware Verification Language).

 

[gentle_man]

"System-on-a-Chip Verification - Methodology and Techniques" is a useful book for you

 

[tom123]

In general project, verification process will cost 60%

of project time, so design for verfication is payoff.


best regards

What do u mean by design for verification

 

[mopengfei]

the book <writing testbench>
and the <Principles of Verifiable RTL Design> are very good --
but i recommand this book for you ---if you are the newboy
<professional verification ------a guide to advanced functional verification>


you can read this book first, and then read the < writing testbench>

 

[stocking]

I suggest two books for your reference.
1. Writing testbenches : functional verification of HDL models
2.Principles of verifiable RTL design : a functional coding style supporting verification processes in Verilog


who has the books ? pls share them! thanks !!!

 

[jjww110]

where can i find the book "System-on-a-Chip Verification - Methodology and Techniques" ??

 

[reddy]

the book <writing testbench>
and the <Principles of Verifiable RTL Design> are very good --
but i recommand this book for you ---if you are the newboy
<professional verification ------a guide to advanced functional verification>


you can read this book first, and then read the < writing testbench>

I too am interested in DFT/DFV. Let me know where can I get these books. Are these eBooks?

 

[dearjohn]

writing testbench

System-on-a-Chip Verification

 

[zhaoyimiao]

In short, you should design your testbench and vectors in paralle with you RTL design and you need to design some addtional logics for self testing. DFT compiler also will be helpful for the final check.

 

[Arnold]

I think rtl with well coded structural assertion is some kind of DFV

 

[bzaki]

Hello,
I would like to ask a question?

What is the difference between Design for verification and using scripts (TCL, perl) for verification?

 

[bismillah]

It can mean either, the Design which is to be verified, or it may mean creating verification environment,i.e. writing behavioral models, and test pattern generation, so as to verify the DUT.

 

[amaccormack]

Design for verification is getting the designers who write the RTL to use assertions, documenation, comments, meaningful signal names that dont change as they go up and down the hierarchy, and other best practices to make the verification of the design easier and quicker. It also helps design reuse, too.

 

[tarkyss]

I think DFV means that you must consider verification problem even when you design other than when you begin to verification