Hi,
SETUP analysis:
The STA tool is used to ensure that the data arriving at the flop input is not arriving in the setup window.
In order to ensure it, the STA tool checks that (Arrival time) < (MAX_DELAY – Tsetup)
HOLD analysis:
The STA tool is used to ensure that the data arriving at the flop input is not arriving in the hold window.
In order to ensure it, the STA tool checks that (Arrival time) > (MIN_DELAY +Thold)
Consider the Violation Scenario example:
MAX_DELAY = 12
Arrival time = 11.97 (thus we meet the max delay constraint)
Arrival time of clock at the CK pin of FLOP = 12 (for example this is the first clock edge that comes after data arrival , this value cannot be less than 12, thus this is critical point value)
Setup time of flop = 0.18 (for example)
Thus we see that the time difference b/w clock arrival and data arrival is = 12 -11.97 = 0.03
But the setup time of flop is 0.18
Therefore we see that data is arriving in the setup window of flop. (which is a basic fundamental and is a violation)
We will never be able to catch this violation if we use “12” and NOT “12-setup” for checking setup violation.
Using 12-setup would flag a violation which we will have to FIX
Similar explanation goes for hold
--
Shobhit