Continue to Site

# What define the maximum speed of operation of the digital circuits

Status
Not open for further replies.

#### Junus2012

Hello,

I am working with a digital buffer driver, I need it for applications that require the buffer to drive a pulse with 100 MHz but the on time is 2 nS only.

When I am searching a buffer in the market and read the data sheet, I understand the meaning of the basics propagation delay, rising time and falling time, they even explain it very well in the data sheet. However, I can not interpolate these values to my demand.

So which one of the parameters I should consider? I have seen many people defining the maximum speed of operation as fmax=1(trise+tfall), and so I can't see where is the propagation delay here in the formula. Also, I believe that output logic should be stable for some time before accepting the next change.

I found SN74AHC367N from Texas Instrument, it has a propogation delay of 4.7 nS and trise=tfall = 3 nS

Best Regards

In a behavioral description, propagation delay isn't related to switching speed of a single gate, at least if it's symmetrical. It comes into play when you analyze multi gate circuits.

For a buffer, rise- and fall time are the parameters of primary interest. I presume you noticed that they depend on load capacitance.

To select a suitable buffer, you want to specify load, input- and intended output waveform.

Junus2012

### Junus2012

Points: 2
Hi there,

By definition, rising and falling edge (also called "slew time") is a measure of time passed between 10% and 90% of your VDD/HIGH voltage (have seen 20% and 80%, too) for rising edge (vice versa for falling edge). You can calculate your "slew rate" measured in V/us or V/s, if you need.

T_ON and T_OFF are measured at 50% of VDD/HIGH voltage.

Propagation delay is also defined as a time passed between output and input at 50% of your VDD/HIGH voltage.

THEORETICAL minimum T_ON (or pulse width) can be defined as t_rise + t_fall. Meaning the driver will rise and fall immediately, so you measure the time passed at 50% of that signal voltage. It is only theoretical limit because, as you said, many digital systems require specific minimal pulse width, minimal setup and hold time for flip-flops, etc.
This output signal as a whole will be delayed by propagation delay given by datasheet (measured also at 50% of your signal)

Hope this helps.

Shlooky

Last edited:
Junus2012

Points: 2

Regards, Dana.

Junus2012

### Junus2012

Points: 2
Hi,

an interesting question.

One thing to consider:
If you want transfer information from A to B (example: UART) you don´t have to care about delay.

But if you want the information to come back (feedbacked: Like read a RAM, where you send the ADDRESS and get back DATA) you have to care about delay.

Klaus

Junus2012

### Junus2012

Points: 2
Prop Delay is of course of concern, when do you trust the output of
logic circuits to present correct signaling and state to downstream circuits.

COM link delay of course in feedback loops matters. Even in open loop
architectures where COM is used to signal to local processes the state
of various process inputs.

Regards, Dana.

Junus2012

### Junus2012

Points: 2
Where is your receiver? Is it close to your chip on the same pcb? Or, you have to transfer your pulses through long line (like concentric cable)?
You may to have thing about matching.

### Junus2012

Points: 2
I once had the same problem back in the late 70's using two 10MHz signals to measure Doppler Azimuth so I used a discrete solution.

If you think about it. This is just an analog switch being used at logic levels. No matter what switch you choose you cannot be 100% satisfied unless you meet specs. That is the perfect design. Just to meet specs. Then you must decide what are the "must have" attributes or "specs" for this switch.

Impedance of {source, traces & load} R+C+L , Zo & tolerances. You will want controlled impedances at one end at least!
Thresholds Vol, Voh, tolerances
t_prop @ 50% or @ thresholds
t risetime 10~90% @ xx pF

Once you define these then many options may disappear, so choose wisely and define the purpose as there may be better ways to define specs.

Generally, for high speed > 1GHz logic, current-mode logic (CML) such as ECL is used. Although ECL is 5 decades old and is going obsolete. There is still stock, now but preference for negative supplies can be positive. The advantage is constant differential currents cancel out so no EMI.

Then there are discrete solutions.
Where are your specs and why are you not using CML if you do not need 3.3V swing.

Also please use ns, ps not nS.
Keep in mind CPU's that run at x GHz do not operate more than 1.5V typically < 1V. This reduces the power consumption.
--- Updated ---

I wish I had this simulator 50 yrs ago.

Here I made a 4 pin DIP buffer with 2mm leads around 0.5 nH (not a perfect model)
The wires cap , switches and generator are ideal with infinite bandwidth.

Reset the plots , click the switches, change values and get a feel for what happens to the output voltage and input current. Then use Transmission Line Theory to explain it to yourself.

Hint: although 3.6Vlogic is typically 22 Ohms there is a wide tolerance with Vdd and temperature. By matching the source with an ideal SMD resistor ( no inductance of ~ 0.5 nH/mm +/-50%) the output SNR improves radically by eliminating the resistive reflections only. ( ideal matching requires conjugate impedance. Very low trace impedance requires very thin dielectric. Ribbon ~ 200 ohms.

The 1pF load significantly affects as expected dV/dt = Vdd / RC

Last edited:

Points: 2