u24c02
Advanced Member level 1
Hi.
As I know, basically, we do synthesis in worst case(Max delay data path, Min delay clock path).
But I want to know that what if I use clock gating then what constraints are needed to my sdc?
What kinds of aspects are needed to consider to synthesis within clock gating ?
Is this only functionality problem?
As I know, basically, we do synthesis in worst case(Max delay data path, Min delay clock path).
But I want to know that what if I use clock gating then what constraints are needed to my sdc?
What kinds of aspects are needed to consider to synthesis within clock gating ?
Is this only functionality problem?