What caused the Low test coverage in DFT?

[jasonwj]

Hi all,
I have a trouble(low test coverage) when i run DFTC after sythesis.
my design have 3 blackboxs (rom and ram).
the warning informations as follows:

In all_dft mode...
Pre-DFT DRC enabled
Warning: The trip points for the library named USERLIB differ from those in the library named slow. (TIM-164)
Warning: The trip points for the library named USERLIB differ from those in the library named slow. (TIM-164)
...........................
Information: Starting test design rule checking. (TEST-222)
Warning: Cell i_mc8051_ram has no function specification.
Warning: Cell i_mc8051_rom has no function specification.

.............................
Begin Modeling violations...

Warning: Cell i_mc8051_ram (RF1SH_128x8) is unknown (black box) because functionality for output pin Q[7] is bad or incomplete. (TEST-451)
Information: Cells with this violation : i_mc8051_ram, i_mc8051_ramx, i_mc8051_rom. (TEST-283)


DRC Report

Total violations: 3

-----------------------------------------------------------------

3 MODELING VIOLATIONS
3 Cell has unknown model violations (TEST-451)

Warning: Violations occurred during test design rule checking. (TEST-124)

-----------------------------------------------------------------
Sequential Cell Report

0 out of 603 sequential cells have violations


.............................................................
------------------------------------------------

Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 45562
Possibly detected PT 404
Undetectable UD 508
ATPG untestable AU 911
Not detected ND 5977
-----------------------------------------------
total faults 53362
test coverage 86.59%
-----------------------------------------------
Information: The test coverage above may be inferior
than the real test coverage with customized
protocol and test simulation library.




I have add test points(observe and control) for 3 blackboxs(input data/adr bus and output data/adr bus ). all Sequential Cells in the design is covered,
why the test coverage is so low(86%)?
why the ND faults are so many(5977)?

if i removed this 3 blackboxs, the coverage is higher than 98%.

Could anybody to help me to solve this problem?

Thanks.

Jason

jasonwj0304@hotmail.com

 

[eshwartt]

Hi,

There should not be any Blackboxes what so ever in your design while doing DFT.
DFTC doesn't understand the functionality of rams if it is a blackbox.
You should read appropriate test model for rams in your design before running DFTC.

If your rams are not to be tested by design, ask your RTL guy to bypass rams in testmode to improve test coverage.

Any queries let me know....

Regards,
Esh....

 

[hgby2209]

The Following is the tset model or not ?

MODEL
MODEL_VERSION "1.0";
DESIGN "MEM_32X8";
OUTPUT Q[7:0];
INPUT A[4:0];
INPUT CEN;
INPUT CLK;
INPUT D[7:0];
INPUT WEN;
MODE mem_mode = Mission COND(CEN==0),
Inactive COND(CEN==1);


tch_tas: SETUP(POSEDGE) A CLK MODE(mem_mode=Mission);
tch_tah: HOLD(POSEDGE) A CLK MODE(mem_mode=Mission);
tch_tcs: SETUP(POSEDGE) CEN CLK MODE(mem_mode=Mission);
tch_tch: HOLD(POSEDGE) CEN CLK MODE(mem_mode=Mission);
tch_tds: SETUP(POSEDGE) D CLK MODE(mem_mode=Mission);
tch_tdh: HOLD(POSEDGE) D CLK MODE(mem_mode=Mission);
tch_tws: SETUP(POSEDGE) WEN CLK MODE(mem_mode=Mission);
tch_twh: HOLD(POSEDGE) WEN CLK MODE(mem_mode=Mission);
period_tcyc: PERIOD(POSEDGE) CLK ;
tpw_tckh: WIDTH(POSEDGE) CLK ;
tpw_tckl: WIDTH(NEGEDGE) CLK ;
dly_tya: DELAY(POSEDGE) CLK Q ;
ENDMODEL

 

[jasonwj]

Thanks! eshwartt && hgby2209

I set up my libraries environment as follows:

set synthetic_library ""
append synthetic_library $snps "/libraries/syn/dw01.sldb "
append synthetic_library $snps "/libraries/syn/dw02.sldb "
append synthetic_library $snps "/libraries/syn/dw03.sldb "
append synthetic_library $snps "/libraries/syn/dw04.sldb "
append synthetic_library $snps "/libraries/syn/dw05.sldb "
append synthetic_library $snps "/libraries/syn/dw06.sldb "
append synthetic_library $snps "/libraries/syn/dw07.sldb "
append synthetic_library "./lib/RODSHD_32kx8_slow_syn.db "
append synthetic_library "./lib/RF1SH_128x8_slow_syn.db "

# set target library
set target_library ""
append target_library $sc_db_path "/slow.db "
append target_library "./lib/RODSHD_32kx8_slow_syn.db "
append target_library "./lib/RF1SH_128x8_slow_syn.db "

# set link library
set link_library ""
append link_library $target_library " " $synthetic_library


as above,
1) I have linked RAM's and ROM's synopsys models in target_library and
link_library . why DC still report "blackbox"?
2) I have added test_points by commands "set_test_point_element" to bypass the
blackbox, the test coverage has 2% improvement.

3) I have verilog model for simulation, db model for synopsys DC,
You mentioned "test models for ram", what do you mean about this? ram
model for TetraMAX(*.tv) or others?
4) if i only have db model for synopsys DC, what can i do for DFT insertion?
I don't have TetraMax or Fastscan.

thanks,

Jasonwj

 

[eshwartt]

Hi Jason,

Please see my comments in line....

1) I have linked RAM's and ROM's synopsys models in target_library and
link_library . why DC still report "blackbox"?
[Eshwar]: DC/DFTC expects testmodel or CTL models for RAMS and ROMS if you are doing DFT. For Synthesis, Lib is enough but for scan synthesis, CTL models along with libs are needed.
2) I have added test_points by commands "set_test_point_element" to bypass the
blackbox, the test coverage has 2% improvement.
[Eshwar]: It is better to ask your RTL designer to bypass rams if theyrn't needed to be tested.

3) I have verilog model for simulation, db model for synopsys DC,
You mentioned "test models for ram", what do you mean about this? ram
model for TetraMAX(*.tv) or others?
[Eshwar]: I mean CTL models.
4) if i only have db model for synopsys DC, what can i do for DFT insertion?
I don't have TetraMax or Fastscan.
[Eshwar]: Ask lib team to provide CTL models. Read it in dc using read_lib command like read_lib <path_of_.lib> -test_model <path_of_CTL_model>

Regards,
Eshwar.

 

[jasonwj]

Thanks, eshwartt.

jasonwj