what can i do after tmax after gen ATPG - test it with VCS?

[HolySaint]

what can i do after tmax

after gen ATPG
shall i test it with VCS?

 

[santhosh007]

Re: what can i do after tmax

after gen ATPG
shall i test it with VCS?

once you generated the patterns using the Tmax, then you need to verify the patterns with the simulator like VCS,NC VERILOG for chekcing the correctness of the patterns.

 

[HolySaint]

what can i do after tmax

i sim it
but it show me some errors

i think the vector is wrong

can u give me a right pattern and its' sim picture

thank u

 

[santhosh007]

Re: what can i do after tmax

i sim it
but it show me some errors

i think the vector is wrong

can u give me a right pattern and its' sim picture

thank u

if the simualtion fails, you have to check the failures. try running the chain test parallel pattern simualtion. can you be specific wut kind of failures, you are seeing like (exp 0 sim X)?

 

[badola]

Re: what can i do after tmax

have u checked where r u getting errors?????/in capturing or shifting

 

[HolySaint]

Re: what can i do after tmax

$stop at time 0
cli_0 > $xvcsdki
VCD+ Writer X-2005.06-SP1 Copyright 2005 Synopsys Inc.
cli_1 > scope AAA_tmax_testbench_1_16
Current scope is AAA_tmax_testbench_1_16
cli_2 > .
// 0.00 ns : Begin test_setup
// 200.00 ns : Begin patterns, first pattern = 0
// 200.00 ns : ...begin scan load for pattern 0
// 2600.00 ns : ...begin scan load for pattern 5
// 5100.00 ns : ...begin scan load for pattern 10
// 7600.00 ns : ...begin scan load for pattern 15
// 10100.00 ns : ...begin scan load for pattern 20
// 11300.00 ns : Simulation of 22 patterns completed with 0 errors

$finish at simulation time 11300.00 ns
V C S S i m u l a t i o n R e p o r t
Time: 11300000 ps
CPU Time: 0.230 seconds; Data structure size: 0.6Mb
Fri Nov 21 19:38:44 2008

resualt:

 

[santhosh007]

Re: what can i do after tmax

$stop at time 0
cli_0 > $xvcsdki
VCD+ Writer X-2005.06-SP1 Copyright 2005 Synopsys Inc.
cli_1 > scope AAA_tmax_testbench_1_16
Current scope is AAA_tmax_testbench_1_16
cli_2 > .
// 0.00 ns : Begin test_setup
// 200.00 ns : Begin patterns, first pattern = 0
// 200.00 ns : ...begin scan load for pattern 0
// 2600.00 ns : ...begin scan load for pattern 5
// 5100.00 ns : ...begin scan load for pattern 10
// 7600.00 ns : ...begin scan load for pattern 15
// 10100.00 ns : ...begin scan load for pattern 20
// 11300.00 ns : Simulation of 22 patterns completed with 0 errors

$finish at simulation time 11300.00 ns
V C S S i m u l a t i o n R e p o r t
Time: 11300000 ps
CPU Time: 0.230 seconds; Data structure size: 0.6Mb
Fri Nov 21 19:38:44 2008

resualt:

This shows your capture simulation is passing. Where did you see the failures?.

 

[HolySaint]

Re: what can i do after tmax

$stop at time 0
cli_0 > $xvcsdki
VCD+ Writer X-2005.06-SP1 Copyright 2005 Synopsys Inc.
cli_1 > scope AAA_tmax_testbench_1_16
Current scope is AAA_tmax_testbench_1_16
cli_2 > .
// 0.00 ns : Begin test_setup
// 200.00 ns : Begin patterns, first pattern = 0
// 200.00 ns : ...begin scan load for pattern 0
// 2600.00 ns : ...begin scan load for pattern 5
// 5100.00 ns : ...begin scan load for pattern 10
// 7600.00 ns : ...begin scan load for pattern 15
// 10100.00 ns : ...begin scan load for pattern 20
// 11300.00 ns : Simulation of 22 patterns completed with 0 errors

$finish at simulation time 11300.00 ns
V C S S i m u l a t i o n R e p o r t
Time: 11300000 ps
CPU Time: 0.230 seconds; Data structure size: 0.6Mb
Fri Nov 21 19:38:44 2008

resualt:

This shows your capture simulation is passing. Where did you see the failures?.

in the vcs log

what maybe missing?
i was confused......

 

[santhosh007]

Re: what can i do after tmax

$stop at time 0
cli_0 > $xvcsdki
VCD+ Writer X-2005.06-SP1 Copyright 2005 Synopsys Inc.
cli_1 > scope AAA_tmax_testbench_1_16
Current scope is AAA_tmax_testbench_1_16
cli_2 > .
// 0.00 ns : Begin test_setup
// 200.00 ns : Begin patterns, first pattern = 0
// 200.00 ns : ...begin scan load for pattern 0
// 2600.00 ns : ...begin scan load for pattern 5
// 5100.00 ns : ...begin scan load for pattern 10
// 7600.00 ns : ...begin scan load for pattern 15
// 10100.00 ns : ...begin scan load for pattern 20
// 11300.00 ns : Simulation of 22 patterns completed with 0 errors

$finish at simulation time 11300.00 ns
V C S S i m u l a t i o n R e p o r t
Time: 11300000 ps
CPU Time: 0.230 seconds; Data structure size: 0.6Mb
Fri Nov 21 19:38:44 2008

resualt:

This shows your capture simulation is passing. Where did you see the failures?.

in the vcs log

what maybe missing?
i was confused......

in this above posted vcs log, all your 22 patterns are passed without any errors "// 11300.00 ns : Simulation of 22 patterns completed with 0 errors "

suppose if you have an error you will find something like this
0 ck (exp=0, got=x)
0 ckn (exp=1, got=x)
0 d1dqs (exp=0, got=1)
0 d3dqs (exp=0, got=z)
// 82900.00 ns : ...begin scan load for pattern 0, load 2