what are the questions on DRC and LVS?

[gksivas]

Hi to all,

In any job description, they mentioned DRC and LVS. They want the candidate who is good in DRC and LVS.

What r the questions to ask about DRC and LVS in interviews. please anybody answer to this question.[/b]

 

[PaloAlto]

There's nothing special with DRC and LVS. DRC stands for Design Rule Checker https://en.wikipedia.org/wiki/Design_rule_checking

LVS is Layout versus Schematic https://en.wikipedia.org/wiki/Layout_Versus_Schematic

Both are checks for a layout. The first one looks for violations to fabrication rules, the second for mistakes in connections and those kind of errors

 

[rajkumaru]

Hello,
Question on DRC and LVS is nothing but question about layout. This can be anythings like how to draw the layout for pmos, nmos, nand, nor, resistor, capacitor, gaurd ring. If you have better understanding of above then you will care how to avoid DRC and LVS problem while drawing layout

Added after 28 seconds:

Hello,
Question on DRC and LVS is nothing but question about layout. This can be anythings like how to draw the layout for pmos, nmos, nand, nor, resistor, capacitor, gaurd ring. If you have better understanding of above then you will care how to avoid DRC and LVS problem while drawing layout

 

[layoutmaster]

As mentioned before, you are a guy good in DRC and LVS when you do your layout considering in advance the DRC and LVS rules associatad with the process you're working on.

That way, once your job is finishing, you'll have a really short time debugging both checks (or, as an ideal case, you'll be able to get a clean check in your first run) because of your previous strategy focused on DRC adn LVS. Hope this help to clarify.