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IO pin count to see if they are enough for your needs,
IO standards supported,
gate number (logic blocks) so that your project can fit,
speed grade to be able to work at the speed you need,
see if there are DLL, or PLL and if they suite your needs,
packaging and availability or price may be important depending on your project.
Some of these may be easier to see if you actually design your project and compile/fit it using the vendor tool, then it will be very easy to see if the max timing suits you and also the area that is needed so that you can choose the appropriate size fpga
talking of gate count... is there any way to predict the gate count of a design in the initial stages?? cos when we start, we wil definitely have only the overall architecture in place.. how do we get an idea of gate count in the beginning itself?
I think the only way is to actually use the fitter in the vendor tool, even an application like Synplify will only show you an estimation of gates and speed.
It will also depend on the options used with the fitter, you can use speed, balanced, area optimization and the result will be different with every setting.
Hi alex.. the fitter will come into picture only when i have the HDL files ready.. but in the beginnning of the project we will be walking in the dark and there will not be any HDL files.. So then how will we know that X will be the approximate gate count for the design??
If the HDL files are not ready then how can you calculate the area you will need?
Each time you change your code the area needed will change too so you should at least have a prototype code done and then you can calculate a 10% for example (or more) for future changes, i don't think there is another way.
I can't imagine that you can say i want to do the X project and some program show an estimation of the result.
Maybe someone else has more knowledge on the matter.
I assume you have a pretty good idea of the top level block diagram, isn't it? Try to devide these block into entities that you can estimate, i.e. UART, processor (if any), DSP functions, state machines, ...
Then you try to find a device that has enough I/O's, memory, logic to cover all these blocks with enough head room. Now look at the migration path of that device, can it grow and schrink? If you are at the top, you need a bigger package; at the bottom, it can probably fit in a smaller device.
Don't stuck to one vendor: compare the vendors against each other.
These are some practical guidelines that I'm using regularly.
- First check how complex is your design.
- Then try to check if this complexity are ready to use .. i mean any IP which can be easily implemented available freely with FPGA vendors.
- What will be you maximum frequency targeted?
- check how much IO would be required and their standard?
- How much Block RAM(internal memory) requirement?
- Cost of FPGA
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