What are the methods for reducing area?

[quan228228]

Does any methods for reducing area?
or which synthesis commands , variabls are used for optimizing area?


Thanks!

David

 

[amitgangwar_vlsi]

synopsys set_max_area area optimization

hello david.....

there is no command to reduce the area.
you can reduce the hardware by efficient coding.
and at the time of synthesis, you can choose area as a constraint other than time. but in this condition your logic will be slow.

so area depends upon on code which you have written........
there is no command to reduce area..........ok

amit gangwar

 

[deh_fuhrer]

dc compile_sequential_area_recovery

In DC you can use the set_max_area constraint to instruct DC to optimize in such a way to have area lower than the speified value(obviously it depends on design and number of cells available in the library)...

you can also specify during compile run to optimize the logic in such a way to have lowest area:

compile -area_effort high

(It increase runtime tremendously but give lowest area design)...

And last but not the least use latest version of the Synopsys DC tool as they are claiming to have 8-10% lesser area with version 2007.03.SP2.CS2 than the previous release.... (better logic optimization algorithm I guess).....

But dont forget to put your comments regarding the saving in area you have got with these techniques as I need to know that...

Thanks,

 

[quan228228]

reduce area

But dont forget to put your comments regarding the saving in area you have got with these techniques as I need to know that...

Thanks,

There are some tricks in area optimization when synthesis.
1. use command, hdlin_use_cin = true
hidden variable, allows a+b+1 to be implemented with the carry in of an adder instead of a separate adder and incrementor.

2. use buttom - up synthesis

3. especially on adder and multiplier,
sometime, the area of multiplier is larger than normal one, because of critical timing, or driving capacity.

This week, i synthsize a module, one sub module includes a multiplier. when i synthesize the sub module, the gate count of multiplier is about 2000. but the gate count of multiplier is 4000 when i synthesize the parent module.
Later, i adapt button-up method, and set dont touch on sub module. the gate count of multiplier keeps 2000.

David.

Any other experience is welcome.

 

[sam536]

compile_ultra boundary optimization

Hi David,
I hope you are using DC compiler for synthesis. Then below methods are applicable.

1) Set_max_area :
To specify a more realistic max_area constraint, run the
report_area command and after getting some "X" value, you can specify an
area reduction of 15-25% from X to the set_max_area command before running
compile.

If run time is not an issue, put set_max_area constrainint to Zero.

2. set_prefer command :
Understand your target library and find out smaller area cells.

Drive initial mapping to use smaller area cells by using the following
command: set_prefer [get_lib_cell library/low_are_cell]

3. Set compile_sequential_area_recovery to true. It will enable sequential element
reselection, which can contribute to area saving. It will give some times 10% inprovemnet in larger designs.

4. Set hlo_resource_implementation area_only. DC choose implementations of parts based on area settings.
Problem : This is the command which will put you in trouble for timing critical designs and if you have large datapath intensive in your design.

5.Boundary optimization :By enabling BO in DC , it tries optimize beyond
hierarchical boundaries. Optimizations such as inversion push and constant
propagation are enabled.
Problem :It might cause verification problems.

6. ungroup. By default, DC optimizes only within hierarchical
boundaries. If boundaries are eliminated, DC will have more space to optimize and get good area results.

 

[deh_fuhrer]

boundary optimization,synopsis dc tool

Hi David,

2. set_prefer command :
Understand your target library and find out smaller area cells.

Drive initial mapping to use smaller area cells by using the following
command: set_prefer [get_lib_cell library/low_are_cell]

Hi sam,
can you give an example to use this set_prefer constraint..Can we specify more than one cell for this...(or some list have to be given)...
Lets have an example, I have a list of cells (lowArea.lst),how can I specify as an argument, or I have to entered each cell name manually...

Thanks

 

[rsrinivas]

give area optimization techniques + edaboard

the compile_ultra command has to reduce area considerably compared to ordinary compile
check whether u have tat licence.
if u have arithmetic components u can use Designware Components as arithmetic components are the ones which use max area and the designware components are the efficient ones which are provided by synopsys.

one more thing regarding compile -area effort high.
This may reduce ur operating speed....

Regards
Srinivas

 

[quan228228]

set_max_area synthesis

DC variable , like set_max_fanout, set_load influnce the area. you should set the appropriate value.


David

 

[sam536]

how to find gate count for designware component

hi David,
yes. you need to add each cell name separatly as u specify in set_dont_use commands. You can use below metods for your prefered cells.

One method :
set_prefer [get_lib_cell library/low_are_cell_1]
set_prefer [get_lib_cell library/low_are_cell_2]
set_prefer [get_lib_cell library/low_are_cell_3] etc....

Second method :

set_prefer {library/low_are_cell_1 library/low_are_cell_2}

Best of luck

Regards,
Sam

 

[quan228228]

compile_ultra -scan area

for example:

set_prefer [get_lib_cell lib/*1x]

where *1x means low driving capacity, low area.

David

Added after 8 minutes:

one paper for area and timing optimization.

David