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Max corner: PVT- Slow Low High
Min corner: PVT-Fast High Low
Yes. Above correct.
2) I think you only need to check setup in max corner and hold in min corner. I guess if your clock tree is very imbalanced an you worry about clock skew re-distribution in max corner, then you may also need to check hold in max corner. But in that case, you would use the same "slow low high" PVT for hold check because it would still be the worst case.
Your understanding regarding PVT corner is correct.
But when you are doing OCV analysis, consider path between reg to reg, the delay on the data path should be worst delay, the delay of capture clock should be best delay, the delay of the launch clock should be again worst.
The worst delay will get on Max corner and best delay will be on min corner.
This kind of analysis will lead to a too pessimistic results. So what STA tool will does is for given corner it will create two library i.e if you consider max delay corner, it will create worst of worst delay library and worst of best delay library depending upon ocv derate values. Now if consider again the same reg to reg path, the delay on the data path will be worst of worst delay, the delay of capture clock will be best of worst delay, the delay of the launch clock will be worst of worst delay.
OCV, BC_WC are for doing the STA analysis at the chip level, i dont think so these concepts will be used while library characterization,
If am wrong can any correct my words, by saying where these concepts are used while lib char
lib and db s are diff in format, snps tools use db format so as to have min memory and run time advantages, u can use utility lib2db to convert libs to db format, dbs are binary format.
so in overall there are only 4 libs in ur case
worst_min.lib (=worst_min.db ) which corresponds to wrst condition libs
simlary best cond'n libs are two,