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Transition violation only indicate that the timing estimate based on the timing table from the liberty file is outside the table range, so the timing estimation could be pessemitst or optimist.
Usually in a design the STA recipe will set constraints for transition time for data and clock nets.
If the any violate the requirements the toll will report a transition time violation.
Usually you need tight transition time for better performance and power.
If you have bad transition time at the input of any cell that will increase the propagation delay of the cell (as per the delay tables from the .libs).
This can cause setup time violations in your design.
Bad transition time can also increase dynamic power dissipation (crowbar current).
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