What are the files needed for BackEnd design in Cadence First Encounter?

[smith_kang]

hi
i'm using cadence First Encounter.I want to know what all files are needed for Flooppalnning,Placement,Routing.
say i've netlist so what all shud be there in that netlist(generally gate level only or anything else also)
then timing lib which shud i use for MAX and MIN
then LEF is this same for all design or specific.
how to create IO assignment file.

 

[sunms]

BackEnd design

You shall contact with your vendor.

 

[Thomson]

Re: BackEnd design

(1) the script somewhat like the one in Design Compiler used to conduct the timing-driven P&R which describes the clock and input delay and output delay and some exceptional paths and so on.
(2) the target technology files which describes the design rule such as the mental rules, spacing rules and so on and are provided by the technology vendor
(3)the source netlist which is created by your synthesis process

Most important of all, you should practice according to the courses provided by Cadence Inc.

 

[omid219]

BackEnd design

Usually you need these files:

.lib: library file
.tlf: timing file for library cells
.lef: layout information

+ your design constraint file

 

[tony_taoyh]

BackEnd design

For the last reply:

Ususlly, you just need either TLF or LIB file.

You can convert between them...

 

[marksile]

Re: BackEnd design

You use cadence's SE tool when you do IC BackEnd design. You should have some files during Floorplanning ,Placement and Routing.

for example,

1. gate netlist after synthesis and must be .v format, The same, It must have verilog description of very cell including IO cells.
2. TLF or GCF file. If you haven't GCF file,you can't CTS.
3. Constraints file. It descript clock imformation.
4. IO place file. It descript that IO cell should placed site.

It should haven't perfect.

Regards,

 

[ryang]

BackEnd design

For SOC Encounter(First Encounter)
You need:
1. Gate Level Netlist (verilog or vhdl)
2. Timing Library for standard cells. TLF format or LIB format. You can get it from library vendor or foundry
3. Physical Library. LEF format
4. Timing Constraints to do STA. In PKS tcl mode or Synopsys SDC mode(recommended by cadence)
5. IO assignment can be generated within SOC encounter.It has 2 types: order oriented and Coordinate oriented. The latter is recommended. You can also manually edit the IO assignment file acording to the syntax it used.

Added after 2 minutes:

6. Clock Tree Spec file which describe the clock logic struction within the design to do CTS
7. Some floorplan instrument provided by front-end guy to specify some model or macro
8.Some technology file which is used to do sign-off RC extraction and power analysis
9. Noise mode to do Cross talk analysis and fix.

 

[ssuhas26]

Re: BackEnd design

Hi,
What does the macro model file contain?
if u know any format please do let me know.

 

[dhaval4987]

Re: BackEnd design

For SOC Encounter(First Encounter)
You need:
1. Gate Level Netlist (verilog or vhdl)
2. Timing Library for standard cells. TLF format or LIB format. You can get it from library vendor or foundry
3. Physical Library. LEF format
4. Timing Constraints to do STA. In PKS tcl mode or Synopsys SDC mode(recommended by cadence)
5. IO assignment can be generated within SOC encounter.It has 2 types: order oriented and Coordinate oriented. The latter is recommended. You can also manually edit the IO assignment file acording to the syntax it used.

Added after 2 minutes:

6. Clock Tree Spec file which describe the clock logic struction within the design to do CTS
7. Some floorplan instrument provided by front-end guy to specify some model or macro
8.Some technology file which is used to do sign-off RC extraction and power analysis
9. Noise mode to do Cross talk analysis and fix.

How to generate a Constraint file? Or Do we have to 'write' it?

 

[GI]

Re: BackEnd design

Hi dhaval4987,

You have to write it yourself. I also heard that there are constraint generators (e.g. false path generators), however I've never used them.

BR,
Gokhan
---

 

[aravind]

Re: BackEnd design

its better contact vendor to get all required files..