What are the different ways of creating delays in a design?

[research_vlsi]

I have one doubt

what are the different ways to create delays in a design?

Note: The Logic should be synthesisable.

Thanks

 

[lordsathish]

Re: Delay in a design

Could Use a FIFO...
But We could only create Delay of the period equal to the integer Multiples of the clock period.

 

[research_vlsi]

Re: Delay in a design

can u explain briefly about FIFO for delay?
Thanks

 

[cafukarfoo]

Re: Delay in a design

through counter or buffer ring

 

[hiral.kotak]

Re: Delay in a design

Hi,

You can either include a no. of buffers or even numbers of inverters to create delay.

Thanks..

HAK..

 

[viju]

Delay in a design

In many libraries delay cells are available. So no need to use discrete buffers or inverters. You can directly take instance of this cell as per your delay requirment.

 

[research_vlsi]

Re: Delay in a design

Thank you friends for your suggestions

 

[pmat]

Re: Delay in a design

Except from buffers and delay cells, you can use whatever mix of gates you want to create
delays... The only contstraint is that you have to use them in a way that they work in a monotonic way, i.e. during the evaluation of the delay every gate should only go once from 0->1 or from 1->0.

Cheers,
Pavlos

 

[realtek]

Delay in a design

using delay cell that provide by foundary
dont use inv for delay
bacause you cannot control the delay time

 

[hiral.kotak]

Re: Delay in a design

HI,

If you have delay cells from the library, you can use them for the specified delay.

Thanks..

HAK..

 

[lsimeon]

Delay in a design

you can use RC circuit for a delay...