What are the differences between Verilog-A and AHDL?

[kwooks21]

Hi!

I'm starting to study High-level simulation and mixed simulation in Cadence.

But I don't know the differences between Verilog-A and AHDL..

Please briefly explain the differences..

Which one is better for system level simulation?
Which one is better for mixed simulation?

Thanks.

 

[pixel]

ahdl is older version. I think that there should be no significial difference in simulation , but there is a possiblity that ahdl would be not supported in some new versions.

 

[wonbef]

Verilog-A for analog circuit modeling languadge

 

[skyangelo]

Verilog-A for analog design but the block can contains digital part.
But you will need Verilog-AMS for design both analog block and digital blocks apart and its interconnection.

 

[yousafzai]

Is Verilog A available for Xilinx FPGA...

 

[pixel]

VerilogA is more intended for device modelling or simulation of analog circuits. It be usefull to simulate analog parts, before you design it. I dont think that is possible to use it for design, like in the case of digital circuits. There were some attempts, but for some specific cases.