What are the commercial applications of FPGA SOC?

[ntxp]

fpga soc

Dear Group,

Just want to have a survey on the commerical applications of FPGA SOC, those big chips from xilinx and altera, such as VirtexII Pro.

Application ideas or experiences sharing here are appreciated.

ntxp.

 

[Bartart]

Hi!

Most of SOC aplication targets telecommunication applications, such as 3G, 4G industry, networing and ADSL technologie.

I am working on DDC SoC, lot of "DSP horse power" and " multimilion gates"are required that is why I use those big FPGA.

Good luck, Bart

 

[ntxp]

Thanks for your reply.

I am sure DSP applications are some of the popular uses of chip design.

But you use FPGA as prototyping tools or for product deployment?

ntxp

 

[rntsay]

bartart,

how do you configure these big fpga's? (if not connected to jtag cable)

eeproms will need too many. I see xilinx system ace and system sc,
did you use these?

thnx

 

[Bartart]

bartart,

how do you configure these big fpga's? (if not connected to jtag cable)

eeproms will need too many. I see xilinx system ace and system sc,
did you use these?

thnx

Hi!

Hm Unfortunatly I use the small FPGA V2P7 and current x*l*nx eproms are OK.

The way to program this FPGA is also to split prom file, but I don`t use this technique, I don`t like to mess up with msc files.


for ntxp:

I do use them for prototyping and also for product deployment.


happy new year 2003 and good luck, Bart

 

[mab]

Hi

i am going to use an Altera Stratix for a (fast) DSP algorithm.
I am aware that software radios are also a usual application for
big FPGA's

mab

 

[Bartart]

Hi!

Before you decide which FPGA you want to use, be 100% sure if there is available help for selected device from the vendor.

I think X*l*nx is better on this site,

@lter@ is better on the price site 8O

SDR 4 ever

good luck, Bart

 

[TurboPC]

Hi!

Before you decide which FPGA you want to use, be 100% sure if there is available help for selected device from the vendor.

I think X*l*nx is better on this site,

@lter@ is better on the price site 8O

SDR 4 ever

good luck, Bart

Altera said: "We are never going to lose a sale to Xilinx because of price"
Xilinx said: "We are never going to lose a sale to Altera because of price"

Bart is right: check for your local support and check for tools. For DSP applications requiring FIR, I would tend to go with Altera/Stratix because of the DSP blocks with the 'free' adder-tree that goes with it. However, for the same device size, there are more multiplier in Xilinx than Altera.

 

[Jayson]

How can someone estimate how many gates one really needs in a FPGA?
How does someone go about determining this? It seems some of you just pick these numbers up floating in the air.

- Jayson

 

[TurboPC]

How can someone estimate how many gates one really needs in a FPGA?
How does someone go about determining this? It seems some of you just pick these numbers up floating in the air.

- Jayson

In CPLD, there are many product terms and many inputs to a macrocell. If your equations are not too big, you can assume 1 logic cell per flip-flop or equation.

For FPGA, it is a bit more complicate. Just remember there are 4 inputs/1 output and some bonus carry/cascade. You have to determine for each equation how much logic cell an equation will take.

Numbers are not "floating in the air". It results from experience and detailed study of FPGA's architecture for a specific manufacturer.

My suggestion to you is to take a synthetizer tool and practice with some small designs. Try to predict the number of cells and check the resulting equations (not just the amount of lcell) to validate your predictions. With practice, you should easily obtain less than 10% error.

Have fun!

 

[Jayson]

okay if someone has an idea to create a video capture card on PCI using a common codec, how is someone to choose an FPGA to prototype on in the first place? Do you first do all the software on the computer, simulate to your hearts content and the choose an FPGA hoping it will work?

- Jayson

 

[TurboPC]

If you are very unsure of your ressources, use an FPGA device that has many size in the same footprint. At least, you will reduce your risks. You can always put a bigger one later. Look at the Spartan-IIE or the Cyclone.

There are no workaround: either you have an idea of the required ressources, either you design most of it and choose the device afterward.

Video Acquisition Card? Let's proceed by elimination:

1- The analog video interface is generally done by a decoder chip like Philips, NEC, ... and requires very few glue-logic. Only a micro-controller to program the registers using I2C (could be done in FPGA for static or quasi-static configurations).

2- For the PCI interface, it depends if you intend to use a subset of the PCI standard or the full. Many FPGA PCI cores have been designed from various vendor. They will provide also the ressources required for different target devices. One example below.
**broken link removed**

3- The common codec you mentionned is a big unknown. Surely you have something in mind and you plan to use an existing codec already targeted for a device. If not, you have to partition your design in smaller blocks and determine the number of ressources required for each. Yes! It is a long process, but there is no other way.

If you plan to use an MPEG codec, I know there is a 1-chip solution with a PCI interface. Hence you may need only a CPLD for the glue logic.

Good luck!

 

[gladiolus]

Applications of SOC

I've seen them used in all sorts of telecom applications.

Video processing, ASIC code evaluation, set-top boxes, r&d, military applications...

koivu

 

[Bartart]

How can someone estimate how many gates one really needs in a FPGA?
How does someone go about determining this? It seems some of you just pick these numbers up floating in the air.

- Jayson

Go to the links below and you will see how to estimate FPGA gates


**broken link removed**

**broken link removed**

https://www.dacafe.com/DACafe/EDATools/EDAbooks/ASIC/Book/CH15/CH15.4.htm


Bart

 

[ljkong]

thanks. it is so good.

 

[Ohh]

I am not sure whether the programmable SOC devices such as
Xilinx Virtex-II Pro or Altera Excalibur do support partial & run-time reconfiguration of FPGA logic or not. If they can,
it is also possible to implement
a run-time reconfigurable system
that allows us to load and unload
cores into the FPGA fabric, and
this process can be controlled by the embedded processor implemented on the same die.