penchal_gv
Junior Member level 1
Hi Friends,
What are the advantages & disadvantages of stack via in layout?
What are the advantages & disadvantages of stack via in layout?
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Teddy said:I know that in case of larger number of vias it is recommended to stagger them due to stress on metals. So place M1 and M2 offsett and M3 again on M1 etc.
cmos_dude said:Even I encountered a similar DFM guideline for a UMC project.
But could not understand that if the same stacked vias are used to support the metal stress in one process, how can they add stress in the other :?:
--Cmos_Dude
srieda said:cmos_dude said:Even I encountered a similar DFM guideline for a UMC project.
But could not understand that if the same stacked vias are used to support the metal stress in one process, how can they add stress in the other :?:
--Cmos_Dude
Where did you come across saying that stacking vias this way add stress?
cmos_dude said:srieda said:cmos_dude said:Even I encountered a similar DFM guideline for a UMC project.
But could not understand that if the same stacked vias are used to support the metal stress in one process, how can they add stress in the other :?:
--Cmos_Dude
Where did you come across saying that stacking vias this way add stress?
I was just referring to what Teddy had written. But I did encounter the DFM guideline while doing layouts wherein I was not supposed to stack more than three layers of vias.
--Cmos_Dude
solidstate said:Well, the obvious advantage is more compact routing: less chip area and less parasitics. Using stacked vias near gates can introduce a little bit more stress, but usually, if the process allows for stacked vias, there are mostly advantages