perl script for vhdl designer
Since i have migrated recently from Windows environment to UNIX where u use TCL & Perl for scripting is
This is what i found out is
1> TCL: Very closely integrated with ur FPGA Tool. Like u can give ur RTL files to a synthesis tool like Synplify and then use Xilinx par for place and route. This kind of jobs can be easily done using TCL scripts. Also like parameters for synthesis can be specified in some configuration files and u need to read these files and pass the parameters to the synthesis tool like encoding styles, some modes, etc.
2>Perl: Very good scripting language and can be used to parse timing reports, area utilization etc and write this information in a .csv or .xls files.
I am still a newbie in using these languages. But these are some of the things i observed.