[SOLVED] What are 'real' design scenario that need multi cycle path exceptions?

[morris_mano]

After reading about multi cycle paths (MCP), it is clear that whenever the combinational logic takes more than one clock period ( by design) to reach the capturing flop, multi cycle paths are specified.

But, I would like to understand the real design example where this is the case. Could you please give some real design scenario where you had to specify MCP?

I have read in this forum, where they recommended to specify multi cycle paths at CDC capturing flop. Is this a good practise and why?

I have a design where the sub block needs to run at 1/10th slower speed (but in phase) than the system clock. Instead of dividing the clock frequency by 10 for the clock driving the sub block, one way is to assert the enable to all the flops in the sub block every 10th edge of the original clock for 1 clock period. Is this the case of MCP? If yes, how do I specify MCP for all the flops of the sub block?

Thanks,

 

[krishanu007]

I think the example which you have given here for sub-design isnt a MCP case,
MCP is nothing but tool (sta / synth) will give that path 2 cycles for checking violations.
but here you are enabling flops after multiple cycles of the master clock,for driving them with effectively lower frequency.

 

[morris_mano]

Any more design examples where MCP need to be specified?

 

[sam536]

MCP's are driven by Design, not by tools. By protocol, if design want to meet in single cycle and if tool is unable to meet the constraint, you cant put straight away the MCP to 2 or more.

Below are the scenarios :
1. When you multi clock designs , like div by 2. you can meet some times in single clock cycle. Need to have MCP.
2. When you have 64*64 multiplier or etc , which need more time to compute. In these cases , with designers permission, can add MCP.
3. When you are accessing the data from memory elements, the access time will be slow and working at very high speed system clock. Designs will be driven to have MCP since system will wait for 2 or more cycles to fetch the data.
4. When the data accessed in regular intervals of time , data can be utilized/used after few clock cycles, you can add MCP.
5. For the static data (which doesnt used in immediately next clock cycle), you can use MCP.

Many cases can be derived based on the conditions.

Regards, Sam



Regards, Sam

 

[krishanu007]

Is it necessary to have a synchronizer after a multicycle path ?
Isnt it the receiving flop can become metastable at any cycle between initial & last cycle?8-O:-?