What are Netlist and RTL?

[engrbabarmansoor]

Can anyone clearly explain what is netlist and RTL?

 

[research235]

rtl netlist

Hello Engrbabar

The top level design which generally u write in VHDL r verilog. can be RTL level .. but wen u sysnthesis this using synthesis tools like Design compiler we get a gate level netlist. which actually means a list of all interconnects at transistor level.
The RTL is teh top level entry ..

Please let me know if I am wrong ,

suresh

 

[rsrinivas]

what is netlist site:www.edaboard.com

Hello Engrbabar

The top level design which generally u write in VHDL r verilog. can be RTL level .. but wen u sysnthesis this using synthesis tools like Design compiler we get a gate level netlist. which actually means a list of all interconnects at transistor level.
The RTL is teh top level entry ..

Please let me know if I am wrong ,

suresh

it's a list of interconnects at gate and predefined blocks level i think.

 

[maks10]

rtl gate netlist

RTL simply means Register Transfer Logic. As the expansion says it means data is transferred between registers/Flops. Say for example if in a design we want to communicate between two blocks from B1 to B2. Here we transfer data from B1 to a flipflop and then to B2. This way of interfacing is referred as RTL.


Netlist refers to the actual implementation of a particular logic or design &ts interconnections. It can be a pictorial representation (like what we see after synthesis in DC ) or can be a written one like in SPICE. The one we see in DC is gate netlist & in the SPICE is transistor netlist.

 

[mssajwan]

netlist to rtl

Netlist u get after synthesizing RTL.Its a gate level equivalent of RTL(without any delays)

 

[gliss]

what is netlists?

Without delays?
There shouldn't be any delays in RTL or a netlist. Delays are specified by timing information in the library representation of the physical chip.

 

[Raptor]

mux netliste

RTL : Functionality of device written in language like Verilog, VHDL. Its called RTL if it can be synthesized that is it can be converted to gate level description.

Netlist: You get a netlist after you synthesize a RTL. This is gate level description of the device. The high level statements in RTL will be converted to gate level. for example IF being converted to mux....

For timing simultion Netlist is used with SDF(contains delay information)!!!