What are IP Cores (Xilinx) and how can I use them?

[Lykos1986]

What is IP Cores (Xilinx) and how can I use them?

 

[gliss]

xilinx coregen examples

IP Cores are Intellectual Property Cores. They are blocks or modules that have been designed and tested for a specific function such as processors, ethernet interfaces and RAM controllers.
Soft IP cores are in the form of HDL and typically have some kind of license associated with them (GPL or proprietary). Hard cores are synthesized blocks that can be instatiated, placed in your design.
The Xilinx specific cores from Xilinx cost money:
**broken link removed**

You can find free IP cores on sites like Opencores.
https://www.opencores.org/

 

[sree205]

tutorial xilinx ip

Hard IP cores are already fabricated in the fpga. these will not account for any fpga programmable resources. These IPs, even if used or not used, will be a part of FPGA unlike soft IPs. Soft IPs can be synthesized and these will be programmed in the fpga.

 

[Lykos1986]

xilinx ip coregen manual

First of all thanks for the answers.

I have installed the Xilinx Xeb pack 8.1. Did you have any manual – tutorial – e-book about IP Cores and Xilinx Program? Also I have a Spartan 3 development board.

 

[salma ali bakr]

xilinx old ip cores

u can download manuals and tutorials from the xilinx site....

https://www.xilinx.com/support/sw_manuals/xilinx8/download/

or just use any old manuals for previous ISE...almost the same for all

just be sure that it supports ur kit, doesn't have everything

good luck

 

[sree205]

ip tutorial core xilinx spartan 3 board

**broken link removed**

Hi,
open any of the examples in the 7.1 and look for the read me file, it explains how an IP can be added to your existing design. hope this helps.

 

[Lykos1986]

generate ip cores xilinx

Now I have a new problem. When I use the Xilinx Core Generator (Xilinx WebPack 8.1i) and i am trying to generate a core the program says to me...

What i have to do?

 

[sree205]

xilinx ip cores tutorial

i think ur installation directory has a space in it. its not supported by the tool. thats the problem

 

[Lykos1986]

Re: Xilinx IP Cores

Ok, I have created the logic core but what about now? How can use that core in any VHDL project?

 

[mwmah]

Re: Xilinx IP Cores

Don't forget when using Xilinx IP Cores from Coregen, to include the xilinxcorelib library.

 

[Lykos1986]

Re: Xilinx IP Cores

Yes, but what sub-library of the xilinxcorelib library???????

For example:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; < - - - - - -
use IEEE.STD_LOGIC_ARITH.ALL; < - - - - -
use IEEE.STD_LOGIC_UNSIGNED.ALL; < - - - - - -


We dint have any manual or a tutorial about IP Cores and how I can use them in a VHDL project???

 

[EDALIST]

Re: Xilinx IP Cores

xilinx will usually generate an edif file .edn, .edf
you also get a wrapper file .vho, vhd that allows you to use the core in your design.
when adding the wrapper file to xilinx ise project, it will put a question mark around it, you can leave it like this or add an .xcf file to it.