What are differences between clock buffer and buffer?

[dsairajkiran]

Hi all,
What are differences between clock buffer and buffer?

 

[sizzlers]

Re: clock buffer

clock buffer has the same rise and fall times.i.e input transition=optput transition.
it is the must and should condition for clock buffer,but normal buffer may not be.

thanku

sizzler

 

[abhi.roy]

Re: clock buffer

clock buffers are symmetrical.

 

[ubna]

Re: clock buffer

Clock buffers are badly needed in a processor, because the clock spreads all over the processor chip and has to enable every part of the chip.So buffering is needed to boost up the signal and make it to supply the clock signal to every part..

Signal buffers are rarely used for boosting up, because they pass through flops, where they get regenerated. they are used for introducing delays and acquiring inputs from pheripherals..

 

[sim_333]

clock buffer

But can u tell me why clock buffer should have same rise and fall time , how will it affect timing ?

 

[ubna]

Re: clock buffer

Certain digital circuits make use of the clock both at positive and negative edges..

 

[Thinkie]

clock buffer

There are actually two kinds of clock buffers often found in libraries.

One is just regular buffers, that are kind of optimised for better mark/space ratio and less variation from PVT.

The other is actually a dummy kind of clock buffer found in some libraries. This is not a real buffer, but a buffer that will expand to a complete clock-tree during PnR

 

[Hards]

Re: clock buffer

Generally there are separate entity in the library are there like CLKBUF and CLKINV
but
In 65nm liberary there is not any entity like CLKBUF or CLKINV so could anybody tell me which buffer of inverter should we use for clock tree

Hardik

 

[Thinkie]

clock buffer

Are you in PnR or in the Synthesis stage ?

I've seen some vendors use just normal buffers even for clock trees.

 

[gangadharn]

Re: clock buffer

Why clock buffer should have same rise and fall time , how will it affect timing ?
According my understanding, same rise and fall time will help in keeping the clock plus symmetric properties. As we know clock is most import part and we don't like change properties. (rise and falling edged rates.)