What are BlockRAM in FPGAs?

[aasif]

xcv300 project

I have XCV300 Xilinx FPGA and I want to build nearly 6400 Data Register each of 8 bits.

1. Can I use BlockRAM for this purpose?
2. What are BlockRAMs?
3. How can we use BlockRAM?
4. How can LUTs be used for this purpose?

Thanks in advance.

 

[nand_gates]

xilinx using registers, force to use ram

Please check the link below!

https://www.fpga4fun.com/HowFPGAsWork.html

hope this helps

 

[nand_gates]

block ram shift register,

Hint.
Configurable Logic Block (CLB) contains single-port or dual-port RAM. This RAM is
distributed throughout the FPGA and is commonly called "distributed RAM" to distinguish
it from block RAM. Distributed RAM is fast, localized, and ideal for small data buffers,
FIFOs, or register files.

 

[freeinthewind]

synplify ram_style

of course you can.

 

[aasif]

register blockram

But how can this BlockRAM be used?
i.e. 6400 data registers each with 8 bits.

 

[zf0579]

force blockram xilinx

In Altera, There are Megacore, we can use it directly. maybe the xilinx may have the same function.

 

[echo47]

But how can this BlockRAM be used?
i.e. 6400 data registers each with 8 bits.

The Virtex XCV300 has sixteen 4K bit Block SelectRAMs, for a total of 65536 bits. Each one can be configured as 4Kx1, 2Kx2, 1Kx4, 512x8, or 256x16. You need 51200 bits, so you will need to arrange most of the Block SelectRAMs into one big RAM. You can hook them up yourself, or try using the Xilinx Core Generator to build it for you.

 

[nashafi]

I am simply posing the question again . How can i force any synthesis tool to use Block RAM's instead of using distributed RAM's. I am using mentor's Precision RTL. It has an option on how to use distributed RAM but i am looking for the opposite option.


Thanks,

Nauman

 

[echo47]

How can i force any synthesis tool to use Block RAM's instead of using distributed RAM's?

See the Xilinx Constraints Guide. The RAM_STYLE constraint accepts three values: AUTO, BLOCK, or DISTRIBUTED.

 

[arunragavan]

Distributed RAM and BLOCK RAM -- BLOCK RAM Template.

Sure you can use Blocked Ram for this purpose.


Lookup tables are used as distibuted RAM in xilinix Spartan 3 . Each of the CLB consists of 64 - bit single port RAM or 32 bit dual port RAM which is evenly distributed throughout the FPGA.

Since its equally distributed it is refered as Distributed RAM.

Distributed RAM is fast localized and can be used for small bufferings. This Distributed RAM is present in each of the CLB itself. LUT within in the CLB is implemented using a SRAM.There are 2 LUTs withing *SLICEM unit with one used for READ/WRITE Port and the other used only for READ port. The first one writes into the 16X1 SRAM and the other writes independently. Since the read write operation takes place independently this Distributed RAM is considerably fast.

This distributed RAM supports two memory types one being Single port and the other being DUAL port RAM.

Single port : - Read/Write Operation

Dual Port : - Read operation and Read/Write operation


There is also an embedded 16K block RAM. BLOCK RAMs are large block of Dual Ported memory with one Read and Write port, so i guess you cannot Read and Write at the same time like what you could in a Distributed RAM.(I might be wrong correct me if I am ), This might be one good reason why a Distributed RAM is faster than Block RAM.

VHDL and Verilog logic synthesis tools, such as the Xilinx Synthesis Tool (XST) and Synplicity Synplify, infer block RAM based on the hardware described. The Xilinx ISE Project Navigator includes templates for inferring block RAM in your design. To use the templates within Project Navigator, select Edit ! Language Templates from the menu, and then select VHDL or Verilog, followed by Synthesis Templates, RAM from the selection tree. Finally, select the preferred distributed RAM template.

I have uploaded a template for the Block RAM which u can use in XILINX ISE and try to implement.

I hope this might help you.

Note : - * SLICEM : - Consists of LOGIC/ROM distributed RAM Shift register