What applications is this circuit good for ?

[bobbobtan]

Can someone shed some light on this attached circuit ?

(1) What is the transfer characteristic ( Vout vs. Vin ) ?

(2) How does this circuit operates ?

(3) What happens at Vout , A, B, and C when input is reversed ?



Thanks in advance!
Bob

 

[tsanlee]

Can someone shed some light on this attached circuit ?

(1) What is the transfer characteristic ( Vout vs. Vin ) ?

(2) How does this circuit operates ?

(3) What happens at Vout , A, B, and C when input is reversed ?



Thanks in advance!
Bob

I think this curcit is a simple comparator .
V- > V+ Vc=0V Vout=0V
V- < v+ VC=Hi Vout=V+×Rout÷(R+Rout) (if Id(mn3) is small )

The R is ESD issue.


But I don't know the value of R ans Rout
Can you tell me the value and Rout and w/l of MOS ?

 

[JPR]

The circuit looks to me to be an amplifier.

Vout will be Vin*Rout/R.

Here is how I see the operation:

MN2 provides a current of IDC in MP1. The voltage at B will be the voltage at the the minus terminal of Vin minus R*IDC.

The feedback loop caused by MP2 and MN4 will force the voltage at A to be equal to the voltage at B. The current in the resistor will be Vin/R + IDC. Since IDC will be flowing in MP2, that leaves Vin/R flowing in MN4. This will cause Vin*Rout/R voltage drop on Rout.

 

[surianova]

The circuit looks to me to be an amplifier.

Vout will be Vin*Rout/R.

Here is how I see the operation:

MN2 provides a current of IDC in MP1. The voltage at B will be the voltage at the the minus terminal of Vin minus R*IDC.

The feedback loop caused by MP2 and MN4 will force the voltage at A to be equal to the voltage at B. The current in the resistor will be Vin/R + IDC. Since IDC will be flowing in MP2, that leaves Vin/R flowing in MN4. This will cause Vin*Rout/R voltage drop on Rout.

What is the purpose and application of this circuit?

 

[tsanlee]

The circuit looks to me to be an amplifier.

Vout will be Vin*Rout/R.

Here is how I see the operation:

MN2 provides a current of IDC in MP1. The voltage at B will be the voltage at the the minus terminal of Vin minus R*IDC.

The feedback loop caused by MP2 and MN4 will force the voltage at A to be equal to the voltage at B. The current in the resistor will be Vin/R + IDC. Since IDC will be flowing in MP2, that leaves Vin/R flowing in MN4. This will cause Vin*Rout/R voltage drop on Rout.

My Question is :

The feedbback lopop caused by MP2 and MN4 is positive feedback.
So the voltage in A is not equal to B.

 

[JPR]

I am not sure why you say there is positive feedback?

I break the loop at the gate of MN4.

Apply a positive change in voltage at the gate of MN4.
This change will increase the current in Rout. This same current will flow from node A.
The extra current out node A be divided between the resistor, R, and the small signal resistance of MP2 at node A (1/gmMP2).
The voltage across R will increase (node A will become more negative), and the current in MP2 will decrease.
The decrease in current in MP2 will cause the voltage at node C to decrease.

Since the result around the loop has the inverse sign of the applied test voltage, the loop should have negative feedback.

 

[electronrancher]

hey, is this your homework assignment?

it looks like a high side sense amp to me - for example, measuring current through a sense resistor tied to Vcc. and it does operate on negative feedback. mn4 is driven to cancel the extra current through mp2 - that's negative feedback.

basically, the circuit reflects the differential voltage at Vin to the resistor (provided that R1=R2=R3). Since the pmos mirror keeps the voltage at MP2's source equal to the voltage at MP1's source, the differential voltage must flow through the right hand resistor, R.

Additional current in MP2 raises the gate of MN3 until the current through MN4 cancels the extra current through the right hand resistor. Therefore, the current through MN4 is Vin/R and the voltage needed to create this current is (Vin/R)*Rout.

If the inputs are reversed, no output occurrs - sadly, this circuit is unipolar. gate of MN4 is pulled down until MN4 is off. you can reverse the pmos, and attach MN4:G to the other side if you want the other polarity.

Here is a little plot using R1=R2=R3=10k, and -100mV to +100mV sweep. As you can see, if VIN is negative we can't give any output, only 0v. but for positive input it's quite linear.

for an example application that needs high side sensing, see current limited hot swap controllers. but this is just one of many, many apps.