Well-tap cell requirement in finfet and fdsoi

[gargboy]

As in bulk technology, well-tap or say tap cells are used to provide connection to nwell and p-substrate to avoid latchup and to provide body biasing (if require) and in FDSOI and FINFET technology as there is no pnpn structure and if i don't have to provide body bias, do still i need well-tap connection, If yes, why? Please let me know both in FINFET and FDSOI.

 

[dick_freebird]

Neither of these should show traditional latchup (4-layer
structures in the substrate). However single transistor
latching mechanisms do exist.

You may need to give substrate noise currents someplace
to go, that you know is benign, rather than finding their
own way out - less glass breakage that way

 

[gargboy]

Neither of these should show traditional latchup (4-layer
structures in the substrate). However single transistor
latching mechanisms do exist.

You may need to give substrate noise currents someplace
to go, that you know is benign, rather than finding their
own way out - less glass breakage that way

Thanks for reply.

So it means, we need to use welltaps in FDSOI and FINFET, even when there is no biasing. Can you please share any document if you have, for more understanding on this topic.

Regards,
Dheeraj