Wel defined devices' correspondences schematic-layout but LVS-Assura doesn't agree???

[fofo]

Hello,

After successfully passing the DRC I defined the device correspondences between the schematic and the layout and now I'm running the LVS under ASSORA, It seems that the LVS doesn't use the same data base as the DRC cause the results tell there exist a mismatch between the schema and the layout.

How a device can be well defined and for which reason the LVS doesn't see it???
Then how to define pins,on which layer (met1 pin or pin M1 or what)???
There is a generic resistance that I didn't put myself in the scheme nor in the layout, still the LVS sees it somewhere, any idea???
What the LVW window is for, what to do with it???

I would appreciate your help

 

[erikl]

Well, do you expect us to guess what is wrong? Show the appropriate locations of your LVS error in schematic, in layout, and in your correspondence file!

 

[dick_freebird]

Mismatch of connectivity is not the same as failure to
recognize.

It seems you have no training or experience with layout
verification. Getting good at it wants practice and/or
training. You have to learn its peculiar ways of expressing
what's wrong, and you have to begin by fixing the small
identifiable problems hoping that they eliminate or make
clearer, the more complicated / obscure.

Pins are necessary at the top level unless you like watching
the tools guess and flounder. You put them on the layer,
or its pin-purpose partner, of the appropriate feature
with name and directionality matching the schematic.
If you're serious about it, and working a big design, more
net-naming on the schematics all up and down the
hierarchy can really help you figure out what's being
reported (better than some auto-generated netname).

Asserting correspondences is something I rarely have
to do except in circuits that have a high degree of
low level regularity with nonuniform connectivity at
higher levels, where bad topology-swap choices by
the tool can lead it down a blind alley. And bad
correspondence assertions may cause more trouble
than none at all. I'd save all that for when LVS fails
in a way that indicates that sort of problem, and
then assert only correspondences that address the
point(s) of indecision.