mark643
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Hello
I have a question about my design after synthesis.
This is my input pad of clock:
PDIDGZ i_pad_i_clk (.PAD(i_clk) , .C(w_i_clk) );
The weird thing is: The delay of this pad is too large, and my design will have very large timing violation.
The delay is about 170 ns, and all of this kind of delay is happened in the clock of 2-port register file.
This kind of delay didn't happened in single port register file and ROM.
And other input pad is fine, didn't have large delay.
Many thanks
I have a question about my design after synthesis.
This is my input pad of clock:
PDIDGZ i_pad_i_clk (.PAD(i_clk) , .C(w_i_clk) );
The weird thing is: The delay of this pad is too large, and my design will have very large timing violation.
The delay is about 170 ns, and all of this kind of delay is happened in the clock of 2-port register file.
This kind of delay didn't happened in single port register file and ROM.
And other input pad is fine, didn't have large delay.
Many thanks