[SOLVED] Waveform testbench Output Error

[hby01]

Hi. I'm working on this 32-bit kogge stone adder and I can't seem to get the wavform testbench right. The output signals are giving me H'UUUUUUUU and i cant seem to figure out the solution.
my testbench is as follows:

 

[ads-ee]

Since you didn't include the ksa.vhd file, I can only guess that you didn't connect the Sum output in that file, U means Unassigned/Unknown in simulation.

Regards

 

[hby01]

just sent you the ksa.vhd file. Hope you could check it and give me some feedback.

 

[hby01]

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Code VHDL - [expand]
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VHDL code:
 
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:12:20 03/31/2014 
-- Design Name: 
-- Module Name:    ksa - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------

---

 

[TrickyDicky]

try adding G and P to the process sensitivity list in ksa.vhd.

 

[hby01]

I tried adding G and P to process sensitivity list but nothing changed.

 

[TrickyDicky]

Why are you generating a clock? Cin is not a clock according to ksa.vhd
Why have you created an array of std_logic? why not use std_logic_vector? (you're going to make your life difficult)
As signals in the design only change when the input changes, you need to provide enough inputs to allow the output to ripple all the way through G and P.