Oct 24, 2017 #1 S samg Newbie level 4 Joined Oct 16, 2017 Messages 6 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 57 Hi, Is it possible to trace the contents of a reg ("reg" data type in verilog) variable used inside a verilog task in Vivado simulation output? I just want to see the changes in that reg.
Hi, Is it possible to trace the contents of a reg ("reg" data type in verilog) variable used inside a verilog task in Vivado simulation output? I just want to see the changes in that reg.