wat is level triggering of a clock?

Status
Not open for further replies.

Mkanimozhi

Full Member level 4
Joined
Aug 8, 2007
Messages
193
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
3,445
level triggering

Hi,
wat is level triggering of a clock, how to write a code in vhdl,some one pleae give me some example.


regards
kanimozhi.m
 

Re: level triggering

Hi...
Level triggering is nothing but Latches,

process (enable, data_in)
begin
if enable = '1' then
q <= data_in;
end if;
end process;
 

    Mkanimozhi

    Points: 2
    Helpful Answer Positive Rating
Re: level triggering

I guess you mean a level-sensitive latch (which passes input signal to output when clock signal is '1' and holds previous value when clock is '0').

VHDL description of latch:

Code: 
process (CLK,DIN) is
begin
	if CLK='1' then
		DOUT<=DIN;
	end if;
end process;
 

    Mkanimozhi

    Points: 2
    Helpful Answer Positive Rating
Re: level triggering

Why do you want to go for a level triggered latch,
I guess these are the least wanted in a good logic design.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…