Wat does (!==) Verilog operator mean?

[siva_7517]

Hi,

Wat does this verilog operator means (!==):
example

A !== B

 

[no_mad]

verilog question

Hi,

It is A not equal to B, including x and z (Case inequality).
Bits with x and z are included in the comparison and must match for the result to be true.

 

[salma ali bakr]

Re: verilog question

yes
!== is for inequality
comparing logical values of: 0, 1, X and Z
it's one of the "identity operators"

while the != is for inequality
comparing logical values of: 0 and 1 only
it's one of the "equality operators"

 

[phoenixfeng]

verilog question

additionally, !== can't be synthesised
but != is ok

 

[syncom]

verilog question

suggest to use casex , it is synthesisable..