Warnings when simulate RAM based Shiftreg

Warnings when simulate

hi,
I have generated a RAM based Shiftreg (959bit) from ISE10.1i. when I am simulating in model sim, I am getting some warnings.

I have given bellow... I even created corelib and I have compiled all the components it nedded then I simulated, but i am getting like this

When I am simulating I kept my simulation Resolution in "ps".
Can u tell mi how to clear this problem.

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# Loading C:\FPGAdv63LS\Modeltech\win32/../std.standard
# Loading C:\FPGAdv63LS\Modeltech\win32/../ieee.std_logic_1164(body)
# Loading C:\FPGAdv63LS\Modeltech\win32/../ieee.numeric_std(body)
# Loading C:\FPGAdv63LS\Modeltech\win32/../std.textio(body)
# Loading xilinxcorelib.prims_constants_v9_0
# Loading xilinxcorelib.prims_utils_v9_0(body)
# Loading xilinxcorelib.pkg_baseblox_v9_0(body)
# Loading xilinxcorelib.c_reg_fd_v9_0_comp
# Loading work.shift_reg_959(shift_reg_959_a)
# Loading xilinxcorelib.c_shift_ram_v9_0(behavioral)
# ** Note: NOTE: c_shift_ram_v9_0: completed check generics
# Time: 0 ps Iteration: 0 Region: /shift_reg_959/u0 File: F:/PROJECTS/PROGRAMS/CDMA_1023/Shift_Reg/shiftreg_core/c_shift_ram_v9_0.vhd
# Loading xilinxcorelib.c_reg_fd_v9_0(behavioral)
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Re: Warnings when simulate

hi

ISE 10.1 has some problems like that
i thing that problem take place from ISE update files


i suggest you to use ISE 9.1


good luck