Warning :XST: 646 in simple Verilog Design

[hector.j.cabrera]

Hi, I'm new using verilog, so I starter with a simple design of a 4 bit full adder:

module full_adder( a, b, c_in, c_out, sum);
		
		input [3:0] a,b;
		input c_in;
		output reg c_out;
		output reg [3:0] sum;
		
		/*input wire [3:0] a, b,
		input wire c_in,
		output reg [3:0] sum,
		output reg c_out
    );*/

	reg [4:0] sum_tmp;

	always @(a or b or c_in)
	begin
		sum_tmp = a + b +c_in;
		{c_out, sum} = sum_tmp;
	end


endmodule

I try differents port declaration style but I still get the next warning:

WARNING:Xst:646 - Signal <sum_tmp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

What its wrong with the code? how can I remove the warning?

Thanks!

 

[vipinlal]

I think you can simply ignore this warning.The synthesis tool here, is trying to optimize the design and it found that the declared register is not actually not needed for the design to work.See if the code works in simulation.If yes ignore the warning.

I am not sure if this is valid in Verilog, but can you try this?

{c_out, sum} = a + b +c_in;