WARNING:Xst:1290 - Hierarchical block <d_ff0> is uncon

[sriramsv]

xst:1290 - hierarchical block

Hi guys,

I'm getting the below error during Synthesize-XST in Webpack 8.1i. Can anyone tell me what to do. There is no syntax error in my program!!!

WARNING:Xst:1290 - Hierarchical block <d_ff0> is unconnected in block <encoder>


here is my programs

module encoder(mesg,clk);
input [15:0]mesg;
input clk;
//output [15:0]cwd;

wire [15:0]q; // o/p from the buffer i.e D_FF
wire [15:0]s_p; // o/p from the serial to parallel shifter

DFF d_ff0(mesg,clk,q);
SP s_p0(q,clk,s_p);

endmodule



module DFF(mes,clkd,q0);
input [15:0]mes;
input clkd;
output reg[15:0]q0;
always @(posedge clkd)
begin
q0 <= mes;
end

// SP s_p0(q,clk,s_p);
endmodule

module SP(q1,clksp,s_p0);
input [15:0]q1;
input clksp;
output [15:0]s_p0;
reg [15:0]tmp;
//wire [15:0]s_p;
//wire [15:0]mem_in;

assign s_p0 = tmp;
always @(posedge clksp) begin
tmp = {tmp[14:0], q1};
end

endmodule


Thanks

 

[echo47]

vsim-3036 75

That message is a warning, not an error. However, and error occurs later:
ERROR:Map:116 - The design is empty. No processing will be done.

Your "encoder" module has no outputs. It therefore does nothing, so it will be optimized away, along with d_ff0 and s_p0.

 

[sriramsv]

Re: WARNING:Xst:1290 - Hierarchical block <d_ff0> is u

Tanx. I resolved that issue, but now my "Generate Expected Simulation results" shows me the error:
# ** Error: (vsim-3036) Instantiation depth of '/encoder_tbw/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT' is 75. Assuming recursive instantiation.
# Region: /encoder_tbw/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT/UUT
# Error loading design
Error loading design
ERROR: VSim failed to simulate annotated testbench

But the "Simulate Behavioral model" which opens up Model Sim shows me the O/P from the Serial to Parallel Shifter. Can you tell me how to rectify that too!!!! here are my corrected codes

module encoder(mesg,clk,s_p);
input [15:0]mesg;
input clk;
//output [15:0]cwd;

wire [15:0]q; // o/p from the buffer i.e D_FF
output [15:0]s_p; // o/p from the serial to parallel shifter

DFF d_ff0(mesg,clk,q);
SP s_p0(q,clk,s_p);

endmodule



module DFF(mesg,clk,q);
input [15:0]mesg;
input clk;
output reg[15:0]q;
always @(posedge clk)
begin
q <= mesg;
end

// SP s_p0(q,clk,s_p);
endmodule

module SP(q,clk,s_p);
input [15:0]q;
input clk;
output [15:0]s_p;
reg [15:0]tmp;
//wire [15:0]s_p;
//wire [15:0]mem_in;

assign s_p = tmp;
always @(posedge clk) begin
tmp = {tmp[14:0], q};
end

endmodule


Thanks

 

[echo47]

Your new code compiles cleanly in my ISE 8.1i, and ModelSim. Maybe you are not operating the tools correctly. Be sure to tell the tools which module is your top module. I don't like Project Navigator, so I run the tools from the command line with a makefile.

I don't see any serial-to-parallel shift register. Look carefully, this statement simply copies q to tmp, because q is 16 bits wide:
tmp = {tmp[14:0], q};

Also, you should use <= instead of = inside the clocked always block.

Please edit your message and shorten that long /UUT/UUT/UUT string. It is making this web page really wide!