// altera message_off 10000To enable or disable specific HDL messages in your HDL, use the message_on and message_off synthesis directives. Both directives take a space-separated list of Message IDs. You can enable or disable messages with these synthesis directives immediately before Verilog HDL modules, VHDL entities, or VHDL architectures. You cannot enable or disable a message in the middle of an HDL construct.
A message enabled or disabled via a message_on or message_off synthesis directive overrides its HDL Message Level or any message_level synthesis directive. The message will remain disabled until the end of the source file or until its status is changed by another message_on or message_off directive.
but i think it doesnt work with qu(at)rtus II. keep getting error, instead of just warnings.
robinh said:In my point of vue, if you get warnings about ouputs stuck at gnd or vcc, it might reflect the fact that your design generates always zero or one on the corresponding pins.
The warning is here to make you verify if you do not have any misconception in your design (vhdl or schematic), that conducts to this situation.
I think you are wrong;McMurry said:I often get annoying warning of output pins stuck at gnd or vcc.
I know it means no harm, but is there any other coding method that I could get rid of them?
Not necssary. In some cases, you have e. g. a chip enable, that is permantly active in a design. Then you get the warning. With Quartus, there are exactly two warnings for outputs:it usually means you did something wrong if your output stuck vcc/gnd
right, that's why I said 'usually', not 'always' ;FvM said:Not necssary/.../