Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Warning of files VHDL in FPGA design ( ..stx is missing ? )

Status
Not open for further replies.
H

hannachifaten

Member level 2
Member level 2
Joined
May 1, 2013
Messages
44
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,769
Hi every body ,
have you any idea what about this warning :
WARNING:projectMgmt - File C:/....non_file/non_file.stx is missing
i can't synthesize my design even i have simulate this design before but when i come back to continue it has a lot of warning and erros , i don't do any thing


Any answer please
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top