WARNING:HDLParsers:3607 - Unit work/State_Control is now defined in a different file.

[hossam abdo]

when i write the code in vhdl and take a copy of this code in another place
this error appear :
WARNING:HDLParsers:3607 - Unit work/State_Control is now defined in a different file. It was defined in "C:/Users/SH_M_H_A/Desktop/FINAL_LAST_with front end/NEW_CONTROL/State_Control/State_Control.vhd", and is now defined in "E:/HOSSAM/my own/4th year/graduation project/FINAL_CODES/FINAL_LAST_with front end/NEW_CONTROL/State_Control/State_Control.vhd".

how to resolve this warning .because this warning make error in synthesis

 

[ckshivaram]

Xilinx hates relative paths. Always has, probably always will. FWIW, ModelSim can handle relative paths in a project file, but for some reason always defaults to putting in an absolute path. So you have to manually edit the .mpf.

---------- Post added at 07:59 ---------- Previous post was at 07:54 ----------

or

In Xilinx, right click on the container of your source files and click Toggle paths. It switches betweeen relative and absolute paths. You can see on each source file the address into comas.

 

[hossam abdo]

how to edit these files and where are them in files

 

[ic_qiand]

Hi, there

I think u can creat a new project whith includes all ur HDL files, when u move it.

 

[hossam abdo]

sorry, i have little information about organizing the xilinx files.
please. told me the steps to vanish this warning