Warning for open cell library

[kannanunni]

when i use nangate opencell library for syenthesis or1k(openrisc 1000 core), it(RC) gives a warning like this...

Warning : Found CCS construct in the cell. [LBR-408]
: Found 'CCS' construct in file 'NangateOpenCellLibrary_worst_low_ccs.lib', at line 255, column 27.
: Currently, CCS constructs are only parsed & ignored.

what's the reason?
how can i avoid this?

and also i get target slack unconstrained for the whole design..
constraints given to the design is clk : 100MHz

please do help..

 

[ajayg]

you are using the liberty file which is based on CCS model which is not supported by your tool [RTL Compiler] .
Use the liberty files which are based on the NLDM models. This will solve the problem. CCS models are more accurate than NLDM.

 

[kannanunni]

so What is the reason for showing "Target slack unconstrained" after synthesis???
and there also shows no generated clock found for "report clocks -generated" command in RC?

rc:/> report clocks -generated
============================================================
Generated by: Encounter(R) RTL Compiler v09.10-p104_1
Generated on: Jan 25 2011 12:01:28 PM
Module: soc_top
Technology library: NangateOpenCellLibrary revision 1.0
Operating conditions: typical (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================

No clocks to report


but i given a clock constraint like this..

rc:/> report clocks
============================================================
Generated by: Encounter(R) RTL Compiler v09.10-p104_1
Generated on: Jan 25 2011 12:02:19 PM
Module: soc_top
Technology library: NangateOpenCellLibrary revision 1.0
Operating conditions: typical (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================


Clock Description
-----------------

Clock Clock Source No of
Name Period Rise Fall Domain Pin/Port Registers
---------------------------------------------------------------
clk 10000.0 0.0 5000.0 domain_1 0

Clock Network Latency / Setup Uncertainty
-----------------------------------------

Network Network Source Source Setup Setup
Clock Latency Latency Latency Latency Uncertainity Uncertainity
Name Rise Fall Rise Fall Rise Fall
------------------------------------------------------------------------
clk 0.0 0.0 0.0 0.0 0.0 0.0

Clock Relationship (with uncertainity & latency)
-----------------------------------------------

From To R->R R->F F->R F->F
---------------------------------------------------
clk clk 10000.0 5000.0 5000.0 10000.0



Please do reply..