want to know how a testbench differ from verification

[maheshkumar.g]

hi all i am just confused between a verilog testbench and verification since both are used for checking the functionality but in what terms they differ from each other
thanks in advance

 

[rca]

Verification is an activity, the verilog testbench is one way to do this activity.

 

[maheshkumar.g]

Verification is an activity, the verilog testbench is one way to do this activity.

hi rca i am unable to get you can you elaborate with an example

 

[dave_59]

hi all i am just confused between a verilog testbench and verification since both are used for checking the functionality but in what terms they differ from each other
thanks in advance

It might help to explain where you saw these terms. Usually a "testbench" refers the the code you write that is not part of the design being tested (sometimes referred to as the Design Under Test, the DUT). "Verification" is a process in which writing the testbench is just one of many possible tasks under "functional verification", There are many forms of verification including functional, formal, timing, and physical. So your question is very broad to give an answer without the context in which it is being asked.

 

[maheshkumar.g]

It might help to explain where you saw these terms. Usually a "testbench" refers the the code you write that is not part of the design being tested (sometimes referred to as the Design Under Test, the DUT). "Verification" is a process in which writing the testbench is just one of many possible tasks under "functional verification", There are many forms of verification including functional, formal, timing, and physical. So your question is very broad to give an answer without the context in which it is being asked.

hi dave i mean that test bench is written for checking the correctness of the module or design for the respective inputs and formal verification is used to know the bugs,corner cases and etc but i completely dont know the differences my mentor asked that if formal verification is so like finding out the corner cases and the response of the design for the unknown inputs then why dont we write the same cases in verilog testbench and check out instead of doing the formal verification i may be wrong in terms please correct me.....
thank you

 

[dave_59]

It sounds like you are asking the difference between dynamic functional verification using a testbench that provides stimulus and result checking versus static formal verification that exhaustively proves correctness. You might want to see https://verificationacademy.com/topics/formal-based-techniques