Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Time domain equalization is done by using "all pass networks." These are a quad of two left half plane poles and two right hand plane zeros. (You can also use a real LHP pole and RHP zero pair for frequencies near DC.) These produce a time delay near the pole frequency without any amplitude changes. You adjust the real and imaginary parts of the pole-zeros to push up the minimum delay portions of your network. Thre is no easy way to select the optimum parameters. CAD programs do a trial and error method.