vss and gnd pins in layout

[preethi19]

Hi i read somewhere that in some cases vss and gnd are interchangeable. But i want two seperate pins. That of vss and gnd in my layout. But when i do that i am getting an error "label/pin is on a net with a different name". Is there any way i can use both and avoid this error. Thank you!!!!

 

[hobbyckts]

Are you talikng about changing in ORCAD? It is really quite confusing.. It will better if could expalin it clearly.

Why you want to change the pin connections of IC?

 

[starinspace]

Preethi,

I think you are trying to add both the pins VSS and GND in the layout on the same substrate i.e the P+ substrate. As you know the substrate can have only one voltage i,e either VSS or GND. ( Though both voltages are zero, separation is needed to provide star connection to particular set of devices whose each other's noise should not affect each other!)

When you have to provide two voltages to p substrate in the layout you have to virtually separate the substrates by adding layer called "asub" ( This is virtual separation i.e for lvs tool to consider that the p substrate covered by psub is biased with GND voltage and non-asub substrate is biased by VSS) .

Or you have to use deep nwell to separate the two p substrates.

 

[preethi19]

Oh thank you for the reply. now i understand that i wasnt able to give both becoz it overall goes to one single p substrate. So is it possible to give vss to p substrate and gnd to nwell in pmos. Becoz pmos has a nwell so i can place the gnd pin inside the nwell right. The thing is i am doing layout. And one of the pmos bulk is of lower potential and source is of higher potential thereby the source injects some current into the n substrate giving me a soft connection error. So i have used a p diffusion guard ring around the pmos inside the nwell. I need to gnd this guard ring. I am sure i can't place the gnd outside the nwell and give a metal connection from guard ring to gnd also i guess then i get error as vss is also der. But now i need the bulk of the pmos connected to the drain of another transistor so i don't want to ground the bulk and yet i have to give a gnd connection to the guard ring inside the nwell... how can this be done. So its like bulk getting both drain connection with another transistor and also to gnd. Or is p diff guard ring entirely isolated from the n substrate..

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Also i have two pmos transistors guard ring that needs to be grounded. so is it possible to place the gnd in one transistor's guard ring and connect it with the 2nd transistor ring?? Is there a more efficient way to do this. If the suggestion is to place the gnd outside the nwell and give a metal connection from the both guard rings i need a 'asub' layer as u mentioned. But i don't have anything like that is the LSW. Onlt dnw is der which is as you mentioned deep n-well. So i use rectangle create a dnw and place the gnd pin der and connect the guard rings??? is this right way?? pls help

 

[rangermad]

So i have used a p diffusion guard ring around the pmos inside the nwell. I need to gnd this guard ring

Sounds like you are well on your way to creating a NPN.

 

[rangermad]

Sounds like you are well on your way to creating a NPN.

Oops... that should be lateral PNP

 

[preethi19]

hi i cleared the error for the guard ring. But i still can't figure out how to use Vss and gnd in same layout. I understood the part wer we have to virtually seperate them using 'asub" or "deep n well" but can you please tell me how to build these layers in the layout. I can't find them in LSW. Also there is a layer "dnw" which i thought is deep n well. But still how am i supposed to place the pins. Like should i take my whole design and place it inside the "dnw layer and connect to gnd" and outside the dnw layer i place vss and connect the terminals that require vss connection.. Pls help

 

[eLab Electronics]

If I am understanding correctly you basically want to connect two nets that are at the same potential (gnd & vss).
I have seen this done several ways.
1) Leave them disconnected until the very last step. Then connect them and ignore the error, make gerbers.
2) Use a zero ohm resistor to do the separation
3) Use a net tie which is basically a two pin device with copper trace between them in the "device" footprint.

I am sure there are other way also.

If I dint have it correct sorry